A New Fault Injection Approach to Study
the Impact of Bitflips in the Configuration
of SRAM-Based FPGAs
1Faculty of Engineering I, Lebanese University, Lebanon
2Department of Computer Engineering, University of Balamand, Lebanon
3TIMA Laboratory, INPG, France
Abstract: A new method for injecting faults in the configuration bits of SRAM-based FPGAs is proposed. The main advantages over previous methods are its ability to simultaneously inject several faults or bit-flips in the FPGA by “pipelining” the fault injection process. The design to be tested is divided into modules. The first step in the fault injection technique would be inserting one fault in each of the modules and observing the potential misbehavior of these modules. In the second step the effects on the whole system of the misbehavior of the module are independently evaluated. Using this technique makes possible to inject several faults when reconfiguring the FPGA with the faulty bitstream, while other techniques were able to insert only one fault on each reconfiguration. Thus the speed in which faults are injected is significantly increased and the time needed to conduct the experiment is shortened. A simulation is described to validate the new fault injection process.
Keywords: FPGA, Fault injection techniques, SEU, and fault tolerance.
Received November 20, 2008; accepted May 17, 2009