Vertical Links Minimized 3D NoC
Topology and Router-Arbiter Design
1Department of Electrical and
Computer Engineering, Mahendra Engineering College, India
2Department of Electrical and Computer
Engineering, Karpagam College of Engineering, India
3Department of Mathematics, Amrita
Vishwa Vidyapeetham, India
Abstract: Design
of a topology and its router plays a vital role in a 3D Network-on-Chip (3D NoC)
architecture. In this paper, we develop a partially vertically connected
topology, so called 3D Recursive Network Topology (3D RNT) and using an
analytical model, we study the performance of the 3D RNT. Delay per Buffer Size
(DBS) and Chip Area per Buffer Size (CABS) are the parameters considered for
the performance evaluation. Our experimental results show that the vertical
links are cut down upto 75% in 3D RNT compared to that of 3D Fully connected
Mesh Topology (3D FMT) at the cost of increasing DBS by 8%, besides 10% lesser
CABS is observed in the 3D RNT. Further, a Programmable Prefix router-Arbiter
(PPA) is designed for 3D NoC and its performance is analyzed. The results of
the experimental analysis indicate that PPA has lesser delay and area (gate
count) compared to Round Robin Arbiter (RRA) with prefix network.
Keywords: Network
topology; vertical links; network calculus; arbiter; latency; chip area.