Comparison of the Hardware Implementation of Stream Ciphers

Michalis Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, and Costas Goutis

Electrical and Computer Engineering Department, University of Patras, Greece

Abstract: In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area in an FPGA device. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards, especially wireless communication protocols. The Helix cipher is a recently introduced fast, word oriented, stream cipher. W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems concerning A5/1. The designs were implemented using VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each stream cipher in terms of throughput-to-area ratio. This ratio equals to: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

Keywords: Cryptography, security, stream ciphers, hardware architecture, FPGA implementation.

Received April 27, 2004; accepted July 28, 2004