A Novel Transistor Level Implementation of a High Speed Packet Switch
Shanmugam Arumugam1, Shanthi Govindaswamy2, and Praveen Kumar Boya2
1Bannari Amman Institute of Technology and Science, India
2PSG College of Technology, India
Abstract: High speed packet switches are inevitable for ultra high data rate networking systems. The throughput of these switches has to be ideally 100% for effective utilization of the network. While Output Queued (OQ) switches have the optimal delay-throughput performance for all traffic distributions, they require N-times speed up in the fabric that limits the scalability of this architecture. An Input Queued (IQ) switch is desirable for high speed switching, since the internal operation speed is only slightly higher than the speed of the input lines. However, the input queued switch has the critical drawback that the overall throughput is limited to 58.6% due to the Head-of-Line (HOL) blocking phenomenon. In this paper, we present a novel transistor level implementation of an IQ packet switch, using TSPICE. Our circuit has a regular structure and low transistor count. Our simulation results indicate that the circuit may be used to implement switches working well beyond 1 GHz.
Keywords: High speed packet switches, packet switch schedulers, IQ architecture.