Design and Evaluation of an Input Buffered Packet Switch
Azeddine Bilami1, Mustapha Lalam2, Mehammed Daoui2, and Mohamed Benmohammed3
1 Department of Computing Science, University of Batna, Algeria
2 Department of Computer Science, University of Tizi Ouzou, Algeria
3 Department of Computer Science, University of Constantine, Algeria
Abstract: Many architectures of internet routers, ATM and ethernet switches have been proposed and analysed in literature. Theoretically reliable and valid solutions have been developed to achieve high performances but a lot of them are not feasible in practice for commercial and technological reasons. Few papers develop the implementation and simulation aspects. The objective of this paper is the design of a packet switch with a minimum cost and hardware complexity. We propose an input-queuing architecture using a multistage interconnection network and a simple cell selection policy implemented by hardware. The switch is described and simulated using a VHDL language. Performances in terms of throughput and cell loss are evaluated.
Keywords: Routing, switch, multistage interconnection network, Benes network, self routing, VHDL.
Received June 23, 2004; accepted October 30, 2004
