HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
1Laboratory of Electronics and Information Technology, Tunisia
2Department of Electrical and Computer Engineering, Sultan Qaboos University, Oman
3IMS Laboratory, University Bordeaux I, France
Abstract: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering problems. This filter is used essentially to remove impulsive and Gaussian noise in colour images. In our design we start by implementing the software solution in system on programmable chip context using NIOS-II softcore processor and µClinux as operating system. We evaluate the execution time of the whole filtering process. Than we add a hardware accelerator part. This latter is implemented using fast parallel architecture. Compared to the software solution results, the use of the hardware accelerator improves clearly the filtering speed and maintains the good filtering quality as shown by simulations.
Keywords: Filtering, co-design, FPGA implementation, SoPC, NIOS-II processor.
Received January 1, 2008; accepted September 11, 2008