Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications
Paris Kitsos and Odysseas Koufopavlou
Electrical and Computer Engineering Department, University of Patras, Greece
Abstract: Hardware implementations of bulk encryption units for wireless communications are presented in this paper. These units are based on the Triple DES (TDES) block cipher. The hardware modules can be configured in order to implement either the TDES or the DES block cipher. Three different hardware implementations of TDES are proposed. The first two implementations are based on the pipeline design technique, while the third implementation uses the traditional feedback logic design technique (looping). In addition, the DES block cipher’s S-BOXes have been implemented by Look Up Tables (LUTs) or ROM blocks. Comparing with the LUTs, the ROM blocks implementation approach provides higher performance. But, the LUTs implementation approach is used in cases where the ROM blocks are not available. For high-speed performance applications the loop unrolling architecture is selected. The proposed implementation of this architecture achieves 7.36 Gbps data throughput whilst the 16-stage pipeline 2.45 Gbps. The implementation data throughput which is based on the looping architecture is 121 Mbps, but is used significant less hardware resources.
Keywords: Cryptography, triple-DES, DES, block cipher, S-Box, VLSI implementation.